Performance monitoring is a concept used mainly in connection with the analyzation of computer system performance. A performance monitor system typically includes circuitry to collect data for machine analysis and testing without influencing operation of the computer system during normal operation. The circuitry monitors various signals within the computer system, printed circuit board (PCB), component, or application-specific integrated circuit (ASIC), which is gathered and made available to various data storage, computational, or analyzing devices.
Performance monitoring of a computer system allows specific events to be monitored in order to gauge performance, or take appropriate remedial action when necessary. Many different types of events within the computer system can be monitored, and collected data can be presented to connector pins where it can be read and processed by devices such as logic analyzers.
In one prior art performance monitoring system, a connector pin was dedicated to each signal that was monitored. When monitoring printed circuit boards, this often meant that entire connectors had to be dedicated as a performance monitor connector, increasing the expense of the printed circuit board, and reducing the available area for input/output (I/O) signals. This problem is particularly evident where a performance monitor is integrated into a logic design of a gate array or other ASIC. In such a case, only a predetermined number of array pins are available for a particular package type, and the inclusion of a great number of performance monitor pins greatly reduces the amount of logic available for use in the ASIC.
Other prior art performance monitors did not provide for continuous operation under all circumstances. For example, many performance monitors did not continue to collect new performance data while previously collected performance data was being transferred to the external interface. In other words, the performance monitor stopped collecting data while it provided its captured data to an external data analyzer. Furthermore, prior art performance monitors require that the system clock be stopped before changing any mode of operation for the performance monitor. Therefore, where a different mode of performance monitoring was desired, the system was stopped to change the mode of the performance monitoring, which is obviously disruptive to the normal operational of the computer system.
The performance monitor of the present invention provides more versatility than the performance monitors of the prior art, while improving performance and increasing speed. The performance monitor of the present invention allows a much smaller number of connector pins to provide the same information previously requiring a connector pin for each signal which was monitored. The number of connector pins required can be set to a fixed number thereby eliminating any question as to the number of connector pins which are available for normal use. Furthermore, the present invention provides more accurate data profiles, and increases the overall speed in which collected data can be provided by the performance monitor. This is in part due to a unique mode switching feature which allows the computer system, component, or ASIC to continue to operate normally even during performance monitoring mode switching.
The present invention therefore overcomes the aforementioned and other problems of the prior art by providing a novel performance monitoring system capable of continuous multi-mode operation, while increasing speed and performance using a greatly reduced, and predictable, number of connector pins. The present invention further provides a solution to other problems, and offers other advantages over the prior art.